This invention relates generally to electronic data storage systems that access (read and/or write) data storage memory devices via a data bus, and, more particularly, to an electronic data storage system that can access different types of data storage devices via a data bus that can selectively be terminated or left open-ended as required by the memory storage devices used in the system and to a method for operating such an electronic data storage system.
Computers, work stations, servers and other such systems, herein collectively referred to as systems, use many data storage memory units such as memory modules. Each module typically contains a plurality of individual storage bits that can be accessed, i.e., data can be written into the bits written therein and read therefrom. This is accomplished by the processor through a memory controller which is coupled to the individual storage bits, in the modules, via a data bus comprising a plurality of data query lines coupling the individual data storage bits in each module to the memory controller. As computers and the programs used therein, increased in size and complexity, industry demands for better and faster performance, i.e., faster writing and reading, were met by the creation of several different generations of processors, memory controllers and memory modules.
Memory modules, formed of a plurality of individual memory units, have under gone many transitions. The modules, presently used in such systems are typically Dual In-line Memory Modules, commonly called and hereinafter referred to as DIMMs, that are joined together and coupled to the memory controller via the data query lines to form a data net. The DIMMs presently available, in the marketplace, are typically 168 pin, 64 bit modules that use single data rate 3.3. Volt Transistor-Transistor Logic (3.3 Volt TTL) or 3.3. Volt Complimentary Metal on Silicon (3.3 Volt CMOS) receivers and drivers, hereinafter collectively referred to as 3.3 Volt DIMMs or 3.3V DIMMs. These 3.3V DIMMs are typically connected to data buses without end terminations, i.e., open-ended or un-terminated data buses. Thus, each of the data query lines in the data bus between the individual storage bits in the modules and the memory controller are generally open-ended or un-terminated.
Processors have also been improved and their speed significantly increased. However, this increase in processor speed has not resulted in the fastest possible system speeds because the memory access rate to a system memory, populated by the 3.3V DIMMs, is limited to the front-side bus speed from the processor. For maximum performance the system main memory should operate at a rate faster than the front-side bus clock rate since additional components in the system may also limit or be limited by the memory system access rate. A slow memory access rate prevents the faster processor speeds from being realized and thus is a severe bottleneck. To eliminate this bottleneck, there has now been proposed a solution, wherein new DIMM modules capable of providing data to the processor faster than the memory clock rate are used. These DIMMs are known as Double Data Rate (DDR) DIMMs and as Quadruple Data Rate (QDR) DIMMs. Since the present invention can be used with either of these new DIMMs, they will be hereinafter collectively referred to as DDR (Double Data Rate) DIMMs.
These DDR DIMMs require lower voltages (typically 2.5 volts) than are required by the 3.3V DIMMs and, when arranged in multi-drop nets, also require, single or double ended, terminated data busses. Thus they are not compatible with the older 3.3 Volt systems that use open-ended or un-terminated data buses. New systems capable of using such DDR DIMMs are now being developed. These new systems will, when populated with these DDR DIMMs, have a memory access rate at least twice that of systems using 3.3V DIMMs thereby boosting both system performance and system speed.
Although these new Double Data Rate (DDR) systems, and the older Low Voltage systems, all use DIMMs, the need for data bus terminations and lower voltages required by the new DDR DIMMs prevents the newer systems designed for DDR DIMMs from using the older 3.3V DIMMs.
Because of the wide variety in computer needs, when new systems are being introduced, manufacturers, to maintain their customer base, must continue to manufacture the older systems as they simultaneously introduce the newer systems. This requires the manufacturer to stock different parts to provide both the new and the old systems. This requires an increase in the number of required parts which means inventory, logistical problems, and the possibility of human error in assembly of the systems also increase. Moreover multiple parts, especially when similar, can cause confusion during both manufacture of the initial computer and repair of the computer in the field.
In addition, due to a large investment in these older memories, many users will require, when upgrading to new systems, that their old memories be usable in the new systems to which they are upgrading.
Still further, the new and improved DDR DIMMs systems will typically be more costly and, initially, may not be available in the necessary quantities. By providing a system that can accommodate both the old and new technologies these problems will be mitigated for it will permit the customer to configure the memory portion of his system based on cost and performance.
Therefore, although new systems can be built to use only this new DDR approach, there still exists a need for a system that is capable of operating both the older 3.3V DIMMs and the newer, lower voltage, faster DDR DIMMs. Such an improved system will thus permit a manufacturer to offer and provide a wider range of systems to his customers including the choice of either the newer or the older technologies while reducing his inventory, logistical and assembly problems.
Furthermore the present invention permits a manufacturer to do so without either substantial changes to the basic system or a significant increase in cost.
The present invention is directed to a solution to this problem and permits computer manufacturers to build a data storage system capable of accessing, i.e., reading and writing, not only the new DDR DIMMs but also the older, widely used and readily available 3.3V DIMMs.
Thus, the present invention results in an improved system in which either 3.3V DIMMs or DDR DIMMs can be used.
Accordingly, it is an object of the invention to provide a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the memory controller circuit, used in such memory storage systems, with both the older (3.3V) receiver/driver circuits and double rate (DDR) receiver/driver circuits, means for identifying the type of DIMMs in the memory system coupled thereto, means for selecting either the (3.3V) receiver/driver circuits or the double rate (DDR) receiver/receiver circuits required to access the identified DIMMs, means for adding or removing terminations to the data query lines which interconnect the selected receiver driver circuits to the identified DIMMS and means for changing the data interface and address command voltage levels.
Accordingly, it is a further object of the invention to provide a single memory system that can access either 3.3V DIMMs or DDR DIMMs and provide the proper terminations on the data bus used to access the DIMMs.
These and other objects and features of the present invention will become further apparent from the following description taken in conjunction with the drawings.